This invention relates to data processing techniques and more particularly, to a technique which is effective particularly when applied to an instruction system of a program control type, such as the technique which is effective when utilized for the instruction construction system using operands for execution of an instruction.
Instructions in a program control type system include a 2-operand instruction using two operands for instruction execution, a 1-operand instruction using one operand and a 0-operand instruction not requiring any operand. Among them, calculation of effective addresses of operands must be made twice in the 2-operand instruction, and two methods are known involving the construction of the 2-operand instruction. One involves a method which combines operation codes and information necessary for the calculation of the two operands into one word (an instruction addressing unit; see "Hitachi Microcomputer, Semiconductor Data Book, 8/16-bit Microcomputer", pp. 945-952, published in September, 1982 by Hitachi, Ltd.).
This instruction system provides the advantage that the information necessary for the effective address calculation of operation codes and operands can be decoded simultaneously and the execution speed of the 2-operand instruction is high. However, if the information necessary for the calculation of the two operands are put into the same word together with the operation codes, the width of the operation specification field becomes small so that the number (kind) of different instructions capable of being provided becomes small.
In this case, the bit number of one word can be increased, in principle, in order to prevent a decrease of the number of kinds of instructions. However, this means an increase in the bit number of the information to be decoded simultaneously, and hence the circuit scale of the decoder becomes extremely large.
The other construction system of the 2-operand instruction puts the first operation specification field and the second operand specification field into separate words and executes the instruction by use of a plurality of words. This instruction system can expand the field width of the operation specification field in comparison with the system which puts the first operation specification field and the second operand specification field into the same word, and can therefore increase the number of kinds of instructions. Since this system can reduce the bit number of the data to be decoded at one time, this system also can reduce the circuit scale of the decoder.
In accordance with the conventional system which employs the 1- or 2-operand instruction formed by a plurality of words, however, the word containing the operand specification field is arranged to follow the word containing the operation specification field, that is, the operation word. Accordingly, the operation word is first decoded to know the necessity of address calculation, then the word containing the operand specification field is decoded to calculate the effective address and the operand is fetched on the basis of the calculation result. Thereafter, the instruction is executed. For this reason, the execution speed of the instruction is very low.